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Swati Goel
Harvard University
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Karly Hou
Harvard University
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Ebrahim Songhori
Google DeepMind
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Founder's Pitch
"Leverage VLMs to automate and enhance chip floorplanning through guided placement strategies."
Commercial Viability Breakdown
0-10 scaleHigh Potential
1/4 signals
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3/4 signals
Series A Potential
4/4 signals
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Why It Matters
Current manual and learning-based chip placement processes are time-consuming and are challenged by the complexity of balancing multiple performance objectives while minimizing routing congestion. Automating with effective VLMs can significantly enhance design efficiency and outcomes.
Product Angle
Productize VeoPlace as a plug-in for existing electronic design automation (EDA) tools or as a standalone platform that enhances chip floorplanning with VLM guidance—targeting semiconductor designers and companies.
Disruption
This approach could innovate upon existing EDA tools and potentially replace or augment roles of traditional floorplanning methods reliant on manual design expertise or less efficient models.
Product Opportunity
The semiconductor industry continuously seeks innovations to enhance chip performance while reducing design time. This tool targets a pain point in floorplanning at a time where efficiency is paramount due to the complexities introduced by advanced semiconductor processes. Companies and design houses would invest in such a solution to gain competitive advantages in design cycles and performance.
Use Case Idea
A SaaS tool for semiconductor companies to optimize chip design processes by integrating with existing chip design workflows and utilizing VLMs for enhanced placement efficiency.
Science
The researchers propose VeoPlace, a novel framework that uses Vision-Language Models to guide the placement of macros in chip floorplanning. By utilizing VLMs' spatial reasoning, VeoPlace iteratively proposes macro placements, uses evolutionary optimization to refine them, and employs low-level placement tools to finalize arrangements. This approach does not require VLM fine-tuning and achieves notable performance improvements in benchmark tests.
Method & Eval
The method was evaluated on open-source chip benchmark datasets, where it significantly reduced wire lengths in placements and improved placement quality. It outperformed other methods without requiring the fine-tuning typically necessary for such complex tasks.
Caveats
Reliance on the capabilities of VLMs without fine-tuning may limit broader applicability across diverse chip architectures. Unexpected edge cases in chip designs may reduce efficiency gains.
Author Intelligence
Ikechukwu Uchendu
Harvard University
iuchendu1@gmail.com
Swati Goel
Harvard University
Karly Hou
Harvard University
Ebrahim Songhori
Google DeepMind
Kuang-Huei Lee
Google DeepMind
Joe Wenjie Jiang
Google DeepMind
Vijay Janapa Reddi
Harvard University
Vincent Zhuang
Google DeepMind