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Xingbo Du
Shanghai Jiao Tong University
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Founder's Pitch
"Revolutionizing IC floorplanning with an all-in-one deep reinforcement learning tool for 3D design rule unification."
Commercial Viability Breakdown
0-10 scaleHigh Potential
2/4 signals
Quick Build
4/4 signals
Series A Potential
4/4 signals
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Why It Matters
Integrating complex design rules across multiple layers in 3D ICs has been a bottleneck in chip design processes. Automating this task with AI reduces human error, accelerates development timelines, and potentially enhances the Power, Performance, and Area (PPA) metrics of the final product.
Product Angle
Package RulePlanner into a cloud-based EDA tool for semiconductor companies. Offer a subscription model where users can input their IC designs and design rules, and the tool outputs optimized floorplans.
Disruption
This AI-driven tool could disrupt current EDA software by significantly automating the floorplanning process, replacing manual adjustments and multiple specific tools with a single, versatile solution.
Product Opportunity
The global semiconductor market is projected to reach over $500 billion by 2027. Companies regularly need faster, more reliable design processes to stay competitive, creating a need for efficient floorplanning tools.
Use Case Idea
Develop a software tool for electronic design automation (EDA) that uses RulePlanner to automate 3D floorplanning, reducing design time and improving compliance with IC design rules.
Science
The paper introduces a framework using deep reinforcement learning (RL) to automate the process of floorplanning in 3D integrated circuits (ICs). It unifies the processing of various design rules using matrix representations and incorporates constraints to avoid rule violations directly in the RL's action space, using quantitative assessments as reward signals.
Method & Eval
The method uses matrix representations of design rules and constraints within the reinforcement learning action space. It was evaluated against public benchmarks, showing superior performance in satisfying complex rules and effective zero-shot generalization.
Caveats
Adoption may be limited by the proprietary nature of IC design rules, potential resistance to change from traditional methodologies, and initial integration complexities within existing EDA workflows.
Author Intelligence
Ruizhe Zhong
LEAD Shanghai Jiao Tong University
zerzerzerz271828@sjtu.edu.cn
Xingbo Du
Shanghai Jiao Tong University
Junchi Yan
Shanghai Jiao Tong University
yan-junchi@sjtu.edu.cn