Controller Datapath Aware Verification of Masked Hardware Generated via High Level Synthesis | ScienceToStartup | ScienceToStartup

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References (22)

[1]

MaskedHLS: Domain-Specific High-Level Synthesis of Masked Cryptographic Designs

2024Nilotpola Sarma, Anuj Singh Thakur et al.

[2]

Smooth Passage with the Guards: Second-Order Hardware Masking of the AES with Low Randomness and Low Latency

2023Barbara Gigerl, F. Klug et al.

[3]

Power Side-channel Attack Resistant Circuit Designs of ARX Ciphers Using High-level Synthesis

Founder's Pitch

"A tool that verifies the security of hardware designs generated by high-level synthesis, preventing false positives and detecting HLS-induced flaws."

Hardware Security Verification•Score: 4•View PDF ↗

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Controller Datapath Aware Verification of Masked Hardware Generated via High Level Synthesis

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References (22)

Founder's Pitch

"A tool that verifies the security of hardware designs generated by high-level synthesis, preventing false positives and detecting HLS-induced flaws."

Commercial Viability Breakdown

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Controller Datapath Aware Verification of Masked Hardware Generated via High Level Synthesis

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References (22)

Founder's Pitch

"A tool that verifies the security of hardware designs generated by high-level synthesis, preventing false positives and detecting HLS-induced flaws."

Commercial Viability Breakdown

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